Over the past decades, the MOSFET has continually been scaled down in size. Modern CMOS integrated circuits incorporate MOSFETs with channel lengths of tens of nanometers. Smaller MOSFETs are desirable for several reasons. The principal reason is to pack more devices in a given chip area. Smaller ICs allow more chips per wafer, reducing the price per chip.
Smaller transistors also switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the transistor length, width, and the oxide thickness, and junction depths. However, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate into higher chip speed because the RC delay due to interconnections is more significant.
Several difficulties arise due to MOSFET size reduction. The difficulties include higher subthreshold conduction, increased gate-oxide leakage, increased junction leakage, lower transconductance, lower output resistance, interconnect capacitance, and process variations.
Lightly doped drain (LDD) structures are commonly used in MOS devices. LDD technology relies on sidewall spacers to produce improved source-drain (S/D) diffusion/doping profiles that addresses some of the device difficulties described above. LDD processing comprises a series of steps where the same series of processes are repeated for each transistor being built (e.g., Low Vt NMOS, Low Vt PMOS, High Vt NMOS, and High Vt PMOS). The repeated steps typically comprise a photolithographic pattern (exposing the area to be doped), ion implantation, pattern removal, post pattern removal clean and then the process is repeated. To further improve the transistor characteristics, sidewall spacers on the gate stack of various thicknesses, optimized for forming a particular transistor, have been used. S/D processing follows LDD processing.
Regarding process variations, with MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions including length, width, junction depths, oxide thickness etc., that become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain and thus more variable.
Regarding processing associated with S/D doping, process variations have become increasingly problematic as S/D junction depths have reached ≦40 nm which have been accompanied by increasing dopant levels at the silicon surface, particularly as S/D junctions depths have approached 15 nm. Variations in the thickness of screen dielectric for implanting into the S/D regions, for example, can result in high levels of S/D junction profile variation both locally on each IC die and from IC die to IC die. Etch of the silicon surface in the S/D regions after S/D implantation can also result in significant dopant loss that can lead to additional variation in the S/D doping profiles. Accordingly, new processes for forming S/D regions are needed that reduce process induced variation in the S/D doping profiles.